The present invention relates to scan flip-flop circuits, logic macros, and scan test circuits that do not easily cause hold errors of scan test data at the time of shifting operation of scan testing, and methods for laying out the same.
In recent years, the advancement of miniaturization and increasing integration of semiconductor integrated circuits have necessitated scan test design, which is a technique of design for testability of semiconductor integrated circuits. A conventional scan test circuit and a conventional method for laying out the circuit in the scan test design are described below.
FIG. 10 is a block diagram showing a scan test circuit used in conventional scan test design. In the figure, reference numerals 1, 2, 3, and 4 denote D-type flip-flop circuits for scan testing (hereafter referred to as D-FFs), and reference numeral 5 denotes a combination logic circuit. Output terminals Q of the D-FFs 1 to 4 are connected to the combination logic circuit 5 as well as to scan test data input terminals DT of the next stage D-FFs. Normal data input terminals D of the D-FFs 1 to 4 are connected to the combination logic circuit 5.
FIG. 11 is a timing chart showing the operation of the scan test circuit of FIG. 10 in the normal operation mode. In the figure, reference character CK denotes clock signal that is inputted to clock input terminal CK of the D-FFs 1 to 4, reference character DI1 and DI2 denote signals that are inputted to the normal data input terminals D of the D-FFs 1 and 2 respectively, reference characters DO1 and DO2 respectively denote signals that are outputted from the output terminals Q of the D-FFs 1 and 2, reference characters A1, A2, and B1 denote data, reference character tdelay-1 denotes a signal delay time from the output terminal Q of the D-FF 1 to the normal data input terminal D of the D-FF 2, and reference character thold-1 denotes a data hold time of the D-FF 2.
FIG. 12 is a timing chart showing the shifting operation of the scan test circuit of FIG. 10 in the scan test mode. In the figure, reference character CK denotes clock signal that is inputted to clock input terminal CK of the D-FFs 1 to 4, reference character DT1 and DT2 respectively denote signals that are inputted to the scan test data input terminals DT of the D-FFs 1 and 2, reference characters DO0 and DO2 respectively denote signals that are outputted from the output terminals Q of the D-FFs 1 and 2, reference characters C1 and D1 denote data, reference character tdelay-2 denotes a signal delay time from the output terminal Q of the D-FF 1 to the scan test data input terminal DT of the D-FF 2, and reference character thold-2 denotes a data hold time of the D-FF 2.
In the normal operation mode, when clock signal CK changes, the D-FF 1 latches the data A1 and propagates the data to the output terminal Q and the D-FF 2 latches the data B1 and propagates the data to the output terminal Q. Here, a fter the signal delay time tdelay-1 has elapsed from the change of the data DO0 at the output terminal Q of the D-FF 1, the data DI1 at the normal data input terminal D of the D-FF 2 change. The signal delay time tdelay-1 is determined according to the internal configuration of the combination logic circuit 5.
Next, in the shifting operation of the scan test mode, when clock signal CK changes, the D-FF 1 latches the data C1 and propagates the data to the output terminal Q and the D-FF 2 latches the data D1 and propagates the data to the output terminal Q. Here, after the signal delay time tdelay-2 has elapsed from the change of the data DO1 at the output terminal Q of the D-FF 1, the data DT2 at the scan test data input terminal DT of the D-FF 2 change and a shift register operation is carried out. The signal delay time tdelay-2 is determined according to a wiring line delay time of a wiring line 6 for propagating scan test data that is disposed between the D-FF 1 and the D-FF 2. The wiring line for propagating scan test data that connects the two D-FFs is wired using an automatic placing and routing tool. Thus, a scan test function is obtained.
The above-described conventional configuration, however, has a problem as follows; concerning the two D-FFs 1 and 2, since the output terminal Q of the D-FF 1 is connected to the scan test data input terminal DT of the D-FF 2 only via the wiring line 6 for propagating scan test data, the signal delay time tdelay-2 of scan test data is short and, as a result, the D-FF 2 tends to cause hold errors of scan test data.
In addition, in the normal operation mode, data change at the output terminal Q of the D-FF 1 brings about data change also at the scan test data input terminal DT of the next stage D-FF 2, and consequently, transistors connected to the scan test data input terminal DT are caused to operate in the D-FF 2, consuming extra electric power, which is another problem.
Furthermore, in the two D-FFs, the wiring lines that connect the output terminal Q of the present D-FFs with the scan test data input terminal DT of the next stage D-FFs are wired in metal wiring line regions with the use of an automatic placing and routing tool, and therefore, the degree of congestion of wiring lines in this metal wiring line regions is high, which is still another problem.